1. Technical Field
This disclosure relates generally to integrated circuits and, more particularly to integration of chip-scale packaging input-output bump-connection metallurgy into integrated circuit structures.
2. Description of Related Art
Semiconductor integrated circuits (“IC”) in the state of the art have been able to pack millions of circuit elements into a relatively small die, or “chip”, e.g., having lateral area footprint, e.g., a ¼″ by ¼″. Most ICs are designed with input-output (“I/O”) pads located along the periphery of the chip; some requiring hundreds of such pads.
These pads are then wire-bonded to connect the IC to the macro-world of a printed wire board (“PWB”), also known as printed circuit board (“PCB”), and surrounding discrete elements and other IC electronics on the board. This conventional perimeter-lead surface mount technology (“SMT”) for complex circuitry with appropriate interconnects often requires a chip carrier several times greater in size than the chip itself.
For mobile appliances—e.g., cellular telecommunications products, portable digital assistants (“PDA”), notebook computers, and the like—or applications where physical space for computers and instrumentations is extremely valuable—e.g., aircraft, space shuttles, and the like—individual component size and weight are factors which are critical to successful design. Thus, there is a conflict between a higher density of IC elements on the chip with attendant higher input/output (“I/O”) needs and a simultaneous demands for continuing miniaturization with increased functionality.
Wafer-level packaging (“WLP”), wherein a single IC die and its mounting package are manufactured and tested on a multi-die wafer produced by the IC manufacturer prior to singulation into individual chips, offers many advantages to the chip manufacturer. One WLP solution known in the art is generally referred to in the art as chip-scale packages (“CSP”). Chip-scale packaging technology, where the peripheral pads are connected to I/O solder balls by a redistribution metal layer, provides die-sized packaging, allowing more condensed PCB patterns, also referred to in the art as “land patterns” where elements have a specific area “footprint.”
Exemplary, conventional, chip-scale technology is demonstrated by FIGS. 1A and 1B, taken from Semiconductor International magazine, October 2000, pp. 119–128, “Wafer-Level Packaging Has Arrived,” by Dr. Philip Garrou, illustrating the process 100, FIG. 1A, and resultant structure 102, FIG. 1B, for chip-scale packaging I/O redistribution. As shown in FIG. 1A, “IC” 101 peripheral I/O pads 103 have an electrical redistribution to I/O bumps 107 via known manner processes. Step 100A illustrates the formation of a lower “POLYMER LAYER” 113, FIG. 1B, (e.g., benzocyclobutene, “BCB”) of the chip-scale WLP structure. Step 100B “METALLIZATION” illustrates an I/O electrical re-distribution for the chip 101 by formation of traces 109 from pads 103 leading to a centralized region of the chip. Steps 100C and 100D, “SOLDER MASK,” “UBM,” respectively, illustrate the upper polymer layer 113′, FIG. 1B, formation. The process continues, step 100E, “BUMPS,” with an I/O bump formation step wherein the bumps 107 (e.g., solder balls) are located inwardly from the chip 101 periphery.
Conductive material (such as a metal, e.g., copper) beams 109 (FIG. 1B) are lithographically defined superjacent the chip passivation layer 111, e.g., a plasma nitride or the like, generally referred to in the art as the “topside layer,” and within a protective-covering-stress-absorbing material (e.g., resin, polyimide, or the like) 113, 113′, providing a conventional IC 101. A cross-section of a chip-scale I/O bump-out packaging structure is shown in FIG. 1B. A variety of implementations are described by Garrou. In current wafer-level packaging, these additional layers of the chip-scale package are generally so formed on the wafer after the die fabrication is completed, yielding a plurality of packaged die on the wafer, which has many advantages for the manufacturer. A thereafter singulated die with chip-scale package 115 with eight bumps 107 is illustrated in FIG. 1C, showing that the total footprint is essentially the same as the die area. The present invention relates to further discoveries in this regard.
While chip-scale packaging has many advantages, it may also be recognized by those skilled in the art that in the current state-of-the-art, some die may be too small to accommodate a requisite number of bumps for the input-output requirements of an underlying chip. Moreover, in wafer-scale fabrication or for applications which may take advantage of providing a chip-set device including more than one individual die with appropriate interconnections, it would be advantageous to take further advantage of the process steps as shown in FIG. 1A in constructing appropriate layouts.
Many publications describe the details of common techniques used in the fabrication of integrated circuits that can be generally employed in the fabrication of complex, three-dimensional, IC structures; see e.g., Silicon Processes, Vol. 1–3, copyright 1995, Lattice Press, Lattice Semiconductor Corporation (assignee herein), Hillsboro, Oreg. Moreover, the individual steps of such a process can be performed using commercially available IC fabrication machines. The use of such machines and common fabrication step techniques will be referred to hereinafter as simply: “in a known manner.” As specifically helpful to an understanding of the present invention, approximate technical data are disclosed herein based upon current technology; future developments in this art may call for appropriate adjustments as would be apparent to one skilled in the art.